About MOSIS 2.0

MOSIS is the original multi-project wafer (MPW) service, founded at the USC Information Sciences Institute in 1981, and has delivered more than 60,000 integrated circuit designs over its history. MOSIS 2.0 revives and modernizes this service as the semiconductor fabrication gateway within the DoD Microelectronics Commons, operating as part of the California Defense Ready Electronics and Microdevices Superhub (CA DREAMS). Today, MOSIS 2.0 supports roughly 200 customer engagements and ~50 tapeouts per year, with multi-foundry access spanning advanced CMOS (Intel 18A, TSMC, GlobalFoundries) and compound semiconductor platforms (GaAs/GaN through WIN Semiconductors).

Beyond fabrication access, MOSIS 2.0 conducts sponsored research in device technology, design enablement, and lab-to-fab transition for defense-relevant microelectronics. We are building a research team to deliver on this growing portfolio, and this position will lead it.

Position Summary

The MOSIS 2.0 Scientist will lead the team responsible for the execution of research projects in which MOSIS 2.0 participates. This is a hands-on technical leadership role that owns program delivery from award through closeout: translating statements of work into executable technical plans, directing the experimental and design work, managing milestones and sponsor deliverables, and ensuring programs are delivered on schedule and on budget.

The ideal candidate combines deep technical expertise in semiconductor fabrication, device design, and process design kit (PDK) development with a demonstrated record of delivering results on funded research programs.

Key Responsibilities

Program Execution and Delivery

• Serve as technical lead, PI, or co-PI on awarded programs; own execution plans, milestones, deliverables, sponsor reporting, and program reviews.
• Translate statements of work into detailed technical plans, schedules, and resource allocations across the team.
• Track progress against milestones, identify and retire technical and schedule risks early, and keep sponsors informed through regular reporting and reviews.

Technical Execution

• Direct experimental work across device design, mask layout, tapeouts, fabrication runs, and electrical characterization.
• Lead semiconductor process development and integration in cleanroom and foundry environments, including translating research processes into manufacturable flows.
• Deliver PDK and design-enablement work products: device compact modeling, DRC/LVS deck development, parameterized cells, and EDA flow validation in collaboration with foundries and design customers.
• Guide device design and modeling across CMOS and compound semiconductor (GaN/GaAs) technologies, spanning RF, mixed-signal, and emerging device applications.

Team and Stakeholder Leadership

• Build, manage, and mentor a team of research scientists and engineers; allocate staff across concurrent programs and coordinate with USC faculty, students, and MOSIS operations staff.
• Interface with foundry partners, government sponsors, defense industrial base customers, and CA DREAMS hub partners; represent MOSIS 2.0 at program reviews, working groups, and conferences.
• Contribute technical content to new proposals and program plans as needed.

Required Qualifications

• PhD in Electrical Engineering, Materials Science, Applied Physics, or a closely related field.
• 3+ years of post-PhD experience (industry, national lab, or academic research) in semiconductor device technology.
• Demonstrated track record executing sponsored research programs 
• Hands-on expertise in semiconductor fabrication and process integration (cleanroom experience required).
• Strong background in semiconductor device physics, design, and characterization.
• Excellent written and verbal communication skills, including technical writing for sponsor reports and program reviews.

Preferred Qualifications

• Working knowledge of PDK components and EDA flows (e.g., Cadence/Synopsys/KLayout environments; DRC/LVS; compact models such as BSIM or ASM-HEMT).
• Experience with DoD-sponsored research programs (e.g., DARPA, ONR, Microelectronics Commons) and their reporting/security requirements.
• Familiarity with compound semiconductor technologies (GaN, GaAs, InP), photonics, and/or RF/mm-wave applications.
• Experience contributing to or leading research proposals.

Compensation and Application

• Salary range: The annual base salary range for this position is $165,000 to $200,000. When extending an offer of employment, the University of Southern California considers factors such as (but not limited to) the scope and responsibilities of the position, the candidate’s work experience, education/training, key skills, internal peer equity, federal, state, and local laws, contractual stipulations, grant funding, as well as external market and organizational considerations.

• To apply, submit a CV, cover letter, and contact information for three references.

Minimum Education: Doctorate


Minimum Experience: <1 year

Minimum Skills: Demonstrated record of outstanding research contributions and experience. Proven technical proficiency, exceptional creativity, successful collaboration with others, and independent thought. Strong managerial skills. Demonstrated reputation as an emerging leader in field with sustained performance and accomplishment. Demonstrated ability to conceptualize research directions, exert technical leadership, communicate technical ideas, coordinate individual contributions to a research program, and present research plans and results in a manner that will elicit favorable funding actions.


Preferred Experience: 5 years
Preferred Skills: Nationally recognized reputation for excellence in area of expertise.

                                                  

USC is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other characteristic protected by law or USC policy. USC observes affirmative action obligations consistent with state and federal law. USC will consider for employment all qualified applicants with criminal records in a manner consistent with applicable laws and regulations, including the Los Angeles County Fair Chance Ordinance for employers and the Fair Chance Initiative for Hiring Ordinance, and with due consideration for patient and student safety. Please refer to the Background Screening Policy Appendix D for specific employment screen implications for the position for which you are applying. 

We provide reasonable accommodations to applicants and employees with disabilities. Applicants with questions about access or requiring a reasonable accommodation for any part of the application or hiring process should contact USC Human Resources by phone at (213) 821-8100, or by email at uschr@usc.edu. Inquiries will be treated as confidential to the extent permitted by law.

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